| Rule Violations |
Count |
| Clearance Constraint (Gap=0.2mm) (All),(All) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Width Constraint (Min=0.254mm) (Max=1.27mm) (Preferred=0.508mm) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Hole Size Constraint (Min=0.025mm) (Max=5.08mm) (All) |
0 |
| Hole To Hole Clearance (Gap=0.254mm) (All),(All) |
0 |
| Minimum Solder Mask Sliver (Gap=0.254mm) (Disabled)(All),(All) |
0 |
| Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All) |
0 |
| Silk to Silk (Clearance=0.127mm) (Disabled)(All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Room uPower (Bounding Region = (263.677mm, 112.09mm, 268.834mm, 115.494mm) (InComponentClass('uPower')) |
0 |
| Room uSupply (Bounding Region = (269.621mm, 112.039mm, 274.752mm, 115.494mm) (InComponentClass('uSupply')) |
0 |
| Room uDelay (Bounding Region = (286.029mm, 111.989mm, 290.703mm, 115.494mm) (InComponentClass('uDelay')) |
0 |
| Room lock (Bounding Region = (275.387mm, 111.938mm, 280.01mm, 115.367mm) (InComponentClass('lock')) |
0 |
| Room lockgen (Bounding Region = (280.645mm, 111.938mm, 285.191mm, 115.392mm) (InComponentClass('lockgen')) |
0 |
| Room uVoltage (Bounding Region = (257.785mm, 112.166mm, 262.788mm, 115.468mm) (InComponentClass('uVoltage')) |
0 |
| Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) |
0 |
| Total |
0 |
